The invention relates to read-only memories (ROMs) and to methods for their manufacture.
Semiconductor read-only memories have been implemented in a variety of forms most of which are variations of the traditional insulated gate field effect transistor structure. These memories comprise arrays of MOS transistors which, when read, produce a pre-programmed binary code. In the simplest form, these devices are programmed by permanently turning off selected transistors in the array. A variety of approaches have been used for turning off selected devices in the array. A common approach is to eliminate an essential device feature in the selected transistors during manufacture of the array. Thus polysilicon gates can be left out for the selected devices in the course of patterning the polysilicon layer. The source and drain can be omitted in the step of opening source/drain windows. Selected devices can also be eliminated during metallization. In another embodiment, the threshold voltage of selected devices is adjusted using a threshold adjusting implant. This approach has been successful, and is widely used in the industry. However, it typically involves an added implant step.
A typical ROM device consists of a memory array, usually of NMOS devices, with CMOS devices for the drive, logic and sense circuits.
Consequently the overall technology used in ROMs, as in DRAMs, is CMOS technology. Thus it is important that new developments in ROM device design be compatible with CMOS processing.
I have developed a new approach to programming ROM devices in a CMOS memory device. According to my invention, the steps used for complementary doping of the polysilicon gate layer are also used to program the ROM devices in the memory array. By doping selected MOS gates in the ROM array with doping complementary to the doping of the device channel, the threshold voltage of those selected devices is driven substantially higher, and the selected devices are effectively turned off. In this way the ROM devices can be programmed without added process steps.